LBMD=DISABLED, DUPLEXMD=FULL_DUPLEX, ITSEN=DISABLED, DBGMD=RUN
Module Mode Select
| DBGMD | UART Debug Mode. 0 (RUN): The UART module will continue to operate while the core is halted in debug mode. 1 (HALT): A debug breakpoint will cause the UART module to halt. Any active transmissions and receptions will complete first. |
| LBMD | Loop Back Mode. 0 (DISABLED): Loop back is disabled and the TX and RX signals are connected to the corresponding external pins. 1 (RX_ONLY): Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device. 2 (TX_ONLY): Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX. 3 (BOTH): Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX. |
| DUPLEXMD | Duplex Mode. 0 (FULL_DUPLEX): Full-duplex mode. The transmitter and receiver can operate simultaneously. 1 (HALF_DUPLEX): Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active. |
| ITSEN | Idle TX Tristate Enable. 0 (DISABLED): The TX and UCLK (if in synchronous master mode) pins are always an output in this mode, even when idle. 1 (ENABLED): The TX pin is tristated when idle. If ISTCLK is cleared to 0 and the transmitter is configured in synchronous master mode, the UCLK pin will also be tristated when idle. |